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mosel vitelic 1 v53c832l high performance 3.3 volt 256k x 32 edo page mode cmos dynamic ram preliminary v53c832l rev. 1.6 august 1999 high performance 30 35 40 max. ras access time, (t rac ) 30 ns 35 ns 40 ns max. column address access time, (t caa ) 16 ns 18 ns 20 ns min. extended data out page mode cycle time, (t pc ) 12 ns 14 ns 15 ns min. read/write cycle time, (t rc ) 65 ns 70 ns 75 ns features n 256k x 32-bit organization n edo page mode for a sustained data rate of 83 mhz n ras access time: 30, 35, 40 ns n four cas inputs for byte read and byte write control n low power dissipation n read-modify-write, ras -only refresh, cas -before-ras refresh n refresh interval: 512 cycles/8 ms n available in 100-pin pqfp and 100-pin lqfp packages n single +3.3v 0.3v power supply n ttl interface description the v53c832l is a high speed 262,144 x 32 bit high performance cmos dynamic random access memory. the v53c832l offers a combination of unique features including: edo page mode opera- tion for higher sustained bandwidth with page mode cycle times as short as 12ns. all inputs are ttl compatible. input and output capacitance is signifi- cantly lowered to increase performance and mini- mize loading. these features make the v53c832l ideally suited for a wide variety of high performance computer systems and peripheral applications. device usage chart operating temperature range package outline access time (ns) power temperature mark q tq 30 35 40 std. 0 c to 70 c blank
2 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l family device pkg ( t rac ) speed pwr. v 5 3 c 3 2 30 (30 ns) 35 (35 ns) 40 (40 ns) temp. blank (0 c to 70 c) blank (normal) q (pqfp) tq (tqfp) l 8 832l-01 pin table a 0 ? 8 address inputs ras row address strobe cas 0 column address strobe for first byte (i/o 1 ?/o 8 ) cas 1 column address strobe for second byte (i/o 9 ?/o 16 ) cas 2 column address strobe for third byte (i/o 17 ?/o 24 ) cas 3 column address strobe for fourth byte (i/o 25 ?/o 32 ) we write enable oe output enable i/o 1 ?/o 32 data input, output v cc +3.3v supply v ss 0v supply nc no connect description pkg. pin count pqfp q 100 tqfp tq 100 100-pin pqfp/tqfp pin configuration top view 5 6 7 8 9 10 11 12 i/o4 vcc i/o5 i/o6 vss i/o7 i/o8 vcc i/o17 i/o18 vss i/o19 i/o20 vcc vcc vss i/o21 i/o22 vss i/o23 i/o24 vcc cas0 cas2 we nc nc ras nc nc i/o29 vcc i/o28 i/o27 vss i/o26 i/o25 vcc i/o16 i/o15 vss i/o14 i/o13 vcc vss vcc i/o12 i/o11 vss i/o10 i/o9 vcc nc cas3 cas1 nc nc oe nc a8 a0 a1 a2 a3 vcc nc nc nc nc nc nc nc nc nc nc vss a4 a5 a6 a7 i/o3 vss i/o2 i/o1 vcc nc nc nc nc nc nc nc nc nc nc vss i/o32 i/o31 vss i/o30 1 2 3 4 832h-02 13 14 15 16 17 18 19 20 35 36 37 38 39 40 41 42 31 32 33 34 43 44 45 46 47 48 49 50 96 95 94 93 92 91 90 89 100 99 98 97 88 87 86 85 84 83 82 81 21 22 23 24 25 26 27 28 29 30 76 75 74 73 72 71 70 69 80 79 78 77 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
3 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l absolute maximum ratings* ambient temperature under bias ................................. ?0 c to +80 c storage temperature (plastic) ..... ?5 c to +125 c voltage relative to v ss .................. ?.0 v to +4.6v data output current ..................................... 50 ma power dissipation .......................................... 1.0 w *note: operation above absolute maximum ratings can adversely affect device reliability. capacitance* t a = 25 c, v cc = 3.3v 0.3v, v ss = 0 v *note: capacitance is sampled and not 100% tested. symbol parameter typ. max. unit c in1 address input 3 4 pf c in2 ras , cas , we , oe 4 5 pf c out data input/output 5 7 pf block diagram a 0 a 1 a 7 a 8 sense amplifiers refresh counter v cc v ss 9 i/o 1 address buffers and predecoders x 0 -x row decoders 512 memory array 512 x 512 x 32 column decoders data i/o bus y 0 -y 8 512 x 32 832l-03 i/o buffer oe clock generator we clock generator 256k x 32 cas clock generator ras clock generator i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 8 i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 i/o 16 i/o 17 i/o 18 i/o 19 i/o 20 i/o 21 i/o 22 i/o 23 i/o 24 i/o 25 i/o 26 i/o 27 i/o 28 i/o 29 i/o 30 i/o 31 i/o 32 oe we cas 2 cas 3 ras 8 cas 1 cas 0
4 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc = 3.3v 0.3v, v ss = 0 v, unless otherwise specified. symbol parameter time v53c832l unit test conditions notes min. typ. max. i li input leakage current (any input pin) ?0 10 m a v ss v in v cc i lo output leakage current (for high-z state) ?0 10 m a v ss v out v cc ras , cas at v ih i cc1 v cc supply current, operating 30 130 ma t rc = t rc (min.) 1, 2 35 120 40 110 i cc2 v cc supply current, ttl standby 4 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 30 130 ma t rc = t rc (min.) 2 35 120 40 110 i cc4 v cc supply current, edo page mode operation 30 120 ma minimum cycle 1, 2 35 110 40 100 i cc5 v cc supply current, standby, output enabled 2.0 ma ras =v ih , cas =v il 1 i cc6 v cc supply current, cmos standby 2.0 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v, all other inputs 3 v ss v cc supply voltage 3.0 3.3 3.6 v v il input low voltage ? 0.8 v 3 v ih input high voltage 2.4 v cc +1 v 3 v ol output low voltage 0.4 v i ol = 2 ma v oh output high voltage 2.4 v i oh = ? ma
5 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l ac characteristics t a = 0 c to 70 c, v cc = 3.3v 0.3v, v ss = 0v unless otherwise noted ac test conditions, input pulse levels 0 to 3v # symbol parameter 30 35 40 unit notes min. max. min. max. min. max. 1 t ras ras pulse width 30 75k 35 75k 40 75k ns 2 t rc read or write cycle time 65 70 75 ns 3 t rp ras precharge time 25 25 25 ns 4 t csh cas hold time 30 35 40 ns 5 t cas cas pulse width 5 6 7 ns 6 t rcd ras to cas delay 15 20 16 24 17 28 ns 7 t rcs read command setup time 0 0 0 ns 4 8 t asr row address setup time 0 0 0 ns 9 t rah row address hold time 5 6 7 ns 10 t asc column address setup time 0 0 0 ns 11 t cah column address hold time 5 5 5 ns 12 t rsh (r) ras hold time (read cycle) 10 10 10 ns 13 t crp cas to ras precharge time 5 5 5 ns 14 t rch read command hold time referenced to cas 0 0 0 ns 5 15 t rrh read command hold time referenced to ras 0 0 0 ns 5 16 t roh ras hold time referenced to oe 6 7 8 ns 17 t oac access time from oe 10 11 12 ns 12 18 t cac access time from cas 10 11 12 ns 6,7,14 19 t rac access time from ras 30 35 40 ns 6, 8, 9 20 t caa access time from column address 16 18 20 ns 6,7,10 21 t lz oe or cas to low-z output 0 0 0 ns 16 22 t hz oe or cas to high-z output 0 5 0 6 0 6 ns 16 23 t ar column address hold time from ras 26 28 30 ns 24 t rad ras to column address delay time 10 14 11 17 12 20 ns 11 25 t rsh (w) ras or cas hold time in write cycle 10 10 10 ns 26 t cwl write command to cas lead time 10 11 12 ns 27 t wcs write command setup time 0 0 0 ns 12, 13 28 t wch write command hold time 5 5 5 ns 29 t wp write pulse width 5 5 5 ns 30 t wcr write command hold time from ras 26 28 30 ns 31 t rwl write command to ras lead time 10 11 12 ns 32 t ds data in setup time 0 0 0 ns 14 33 t dh data in hold time 5 5 5 ns 14
6 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l 34 t woh write to oe hold time 5 5 6 ns 14 35 t oed oe to data delay time 5 5 6 ns 14 36 t rwc read-modify-write cycle time 100 105 110 ns 37 t rrw read-modify-write cycle ras pulse width 65 70 75 ns 38 t cwd cas to we delay 26 28 30 ns 12 39 t rwd ras to we delay in read- modify-write cycle 50 54 58 ns 12 40 t crw cas pulse width (rmw) 44 46 48 ns 41 t awd col. address to we delay 32 35 38 ns 12 42 t pc edo fast page mode read or write cycle time 12 14 15 ns 43 t cp cas precharge time 3 4 5 ns 44 t car column address to ras setup time 16 18 20 ns 45 t cap access time from column precharge 19 21 23 ns 7 46 t dhr data in hold time referenced to ras 26 28 30 ns 47 t csr cas setup time cas - before- ras refresh 10 10 10 ns 48 t rpc ras to cas precharge time 0 0 0 ns 49 t chr cas hold time cas -before- ras refresh 7 8 8 ns 50 t pcm edo page mode read-modify-write cycle time 56 58 60 ns 51 t coh output hold after cas low 5 5 5 ns 52 t oes oe low to cas high setup time 5 5 5 ns 53 t oeh oe hold time from we during read-modify write cycle 10 10 10 ns 54 t oep oe high pulse width 10 10 10 ns 55 t t transition time (rise and fall) 1.5 50 1.5 50 1.5 50 ns 15 56 t ref refresh interval (512 cycles) 8 8 8 ms 17 # symbol parameter 30 35 40 unit notes min. max. min. max. min. max. ac characteristics (cont?)
7 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l notes: 1. i cc is dependent on output loading when the device output is selected. specified i cc (max.) is measured with the output open. 2. i cc is dependent upon the number of address transitions. specified i cc (max.) is measured with a maximum of two transitions per address cycle in edo page mode. 3. specified v il (min.) is steady state operating. during transitions, v il (min.) may undershoot to ?.0 v for a period not to exceed 20 ns. all ac parameters are measured with v il (min.) 3 v ss and v ih (max.) v cc . 4. t rcd (max.) is specified for reference only. operation within t rcd (max.) limits insures that t rac (max.) and t caa (max.) can be met. if t rcd is greater than the specified t rcd (max.), the access time is controlled by t caa and t cac . 5. either t rrh or t rch must be satisified for a read cycle to occur. 6. measured with a load equivalent to one ttl inputs and 50 pf. 7. access time is determined by the longest of t caa , t cac and t cap . 8. assumes that t rad t rad (max.). if t rad is greater than t rad (max.), t rac will increase by the amount that t rad ex- ceeds t rad (max.). 9. assumes that t rcd t rcd (max.). if t rcd is greater than t rcd (max.), t rac will increase by the amount that t rcd exceeds t rcd (max.). 10. assumes that t rad 3 t rad (max.). 11. operation within the t rad (max.) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, the access time is controlled by t caa and t cac . 12. t wcs , t rwd , t awd and t cwd are not restrictive operating parameters. 13. t wcs (min.) must be satisfied in an early write cycle. 14. t ds and t dh are referenced to the latter occurrence of cas or we . 15. t t is measured between v ih (min.) and v il (max.). ac-measurements assume t t = 3 ns. 16. assumes a three-state test load (5 pf and a 380 ohm thevenin equivalent). 17. an initial 200 m s pause and 8 ras -containing cycles are required when exiting an extended period of bias without clocks. an extended period of time without clocks is defined as one that exceeds the specified refresh interval.
8 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l truth table notes: 1. byte write cycles cas 0, cas 1, cas 2, or cas 3 active. 2. byte read cycles cas 0, cas 1, cas 2, or cas 3 active. 3. only one of the four cas ( cas 0, cas 1, cas 2, or cas 3) must be active. function ras cas 0 cas 1 cas 2 cas 3 we oe address i/o notes standby h h h h h x x x high-z read: double word l l l l l h l row/col data out read: first byte l l h h h h l row/col i/o 1 ?/o 8 = data out i/o 9 ?/o 32 = high-z read: second byte l h l h h h l row/col i/o 1 ?/o 8 = high-z i/o 9 ?/o 16 = data out i/o 17 ?/o 32 = high-z read: third byte l h h l h h l row/col i/o 1 ?/o 16 = high-z i/o 17 ?/o 23 = data out i/o 24 ?/o 32 = high-z read: fourth byte l h h h l h l row/col i/o 1 ?/o 23 = high-z i/o 24 ?/o 32 = data out write: double word (early-write) l l l l l l x row/col data in write: first byte (early) l l h h h l x row/col i/o 1 ?/o 8 = data in i/o 9 ?/o 32 = x write: second byte (early) l h l h h l x row/col i/o 1 ?/o 8 = x i/o 9 ?/o 16 = data in i/o 17 ?/o 32 = x write: third byte (early) l h h l h l x row/col i/o 1 ?/o 16 = x i/o 17 ?/o 23 = data in i/o 24 ?/o 32 = x write: fourth byte (early) l h h h l l x row/col i/o 1 ?/o 23 = x i/o 24 ?/o 32 = data in read-write l l l l l h ? l l ? h row/col data out, data in 1,2 edo page-mode read first cycle l h ? l h ? l h ? l h ? l h l row/col data out 2 edo page-mode read subsequent cycles l h ? l h ? l h ? l h ? l h l col data out 2 edo page-mode write first cycle l h ? l h ? l h ? l h ? l l x row/col data in 2 edo page-mode write subsequent cycles l h ? l h ? l h ? l h ? l l x col data in 2 edo page-mode read-write first cycles l h ? l h ? l h ? l h ? l h ? l l ? h row/col data out, data in 2 edo page-mode read-write subsequent cycles l h ? l h ? l h ? l h ? l h ? l l ? h col data out, data in 2 hidden refresh read l ? h ? l l l l l h l row/col data-out 2 ras -only refresh l h h h h x x row high-z cbr refresh h ? l l l l l x x x high-z 3
9 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l waveforms of read cycle waveforms of early write cycle ih v il v ras ih v il v cas ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (r)(12) t cas (5) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rad (24) t rah (9) t asr (8) t rcs (7) t rch (14) t rrh (15) t car (44) t caa (20) t cac (18) t t hz (22) t lz (21) ih v il v we oh v ol v i/o 1 -i/o 32 832l-04 v alid da t a-out address t oes (52) rac (19) column address row address t oac (17) t hz (22) ih v il v oe t roh (16) cas0-cas3 ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t csh (4) t rsh (w)(25) t cas (5) t rcd (6) t crp (13) t cah (1 1) t t rad (24) t rah (9) t asr (8) t t wcr (30) t r wl (31) t dh (33) t dhr (46) ih v il v ih v il v ih v il v 832l-05 t t cwl (26) wch (28) t t ds (32) column address v alid da t a-in high-z ras cas0-cas3 we oe i/o 1 -i/o 32 address t car (44) asc (10) wcs (27) wp (29) row address don? care undefined
10 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l waveforms of oe -controlled write cycle waveforms of read-modify-write cycle ih v il v ih v il v ih v il v t rc (2) t ras (1) t ar (23) t rp (3) t crp (13) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rah (9) t asr (8) row address column address t woh (34) t dh (33) t oed (35) ih v il v ih v il v ih v il v 832l-06 v alid da t a-in t ds (32) t rad (24) ras we oe i/o 1 -i/o 32 t csh (4) address t car (44) t t cas (5) rsh (w)(12) t wp (29) r wl (31) t cwl (26) t cas0-cas3 column address row address v v ih v il v ih v il v t rp (3) t crp (13) t rcd (6) t crp (13) t cah (1 1) t asc (10) t rah (9) t asr (8) wp (29) r wl (31) t oed (35) t ih v il v ih v il v ih v il v 832l-07 v alid da t a-out t rac (19) t cwl (26) t t rad (24) t acs t t oac (17) t t dh (33) t oeh (53) t ds (32) hz (22) cac (18) t lz (21) v alid da t a-in ih v il v oh ol ras cas we oe i/o 1 -i/o 32 address t r wc (36) t rr w (37) t ar (23) t csh (4) t rsh (w)(25) t cr w (40) t r wd (39) cwd (38) t a wd (41) t t caa (20) cas0-cas3 don? care undefined
11 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l waveforms of edo page mode read cycle waveforms of edo page mode write cycle v alid d a t a out v alid d a t a out column address ca c (18) t hz (22) t lz hz (22) hz (22) r o w address column address ih v il v ih v il v rp (3) t ih v il v ih v il v oh v ol v t rah (9) t asr (8) t rcs (7) t rch (14) t csh (4) 832l-08 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (r)(12) t cas (5) t cah (1 1) t t ar (23) t cas (5) t cas (5) pc (42) t crp (13) t t column address t t car (44) t cah (1 1) t rcs (7) t rcs (7) t rch (14) t o a c (17) t t o a c (17) t caa (20) t rrh (15) lz (21) t ra c (19) t t ca c (18) t oep (54) v alid d a t a out t crp (13) t t ras we oe address t asc (10) t coh (5) ca c (18) t hz (22) t caa (20) t oes (52) cap (45) t cah (1 1) i/o 1 -i/o 32 cas0-cas3 r o w add ih v il v ih v il v ih v il v ih v il v t t asr (8) 832l-09 ih v il v cp (43) t asc (10) rcd (6) t rsh (w)(25) column address t cah (1 1) t cas (5) t cas (5) t car (44) t rad (24) t cwl (26) v alid d a t a in t crp (13) t wcs (27) wp (29) t cah (1 1) t asc (10) t cah (1 1) t dh (33) t ds (32) ih v il v column address rah (9) column address t crp (13) t t wch (28) t cwl (26) t wcs (27) wp (29) t wch (28) t t cwl (26) t wcs (27) wp (29) t wch (28) t v alid d a t a in t dh (33) t ds (32) v alid d a t a in t dh (33) t ds (32) t rp (3) t ar (23) ras we oe address open open t r wl (31) t t csh (4) t ras (1) t pc (42) t t cas (5) i/o 1 -i/o 32 cas0-cas3 don? care undefined
12 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l waveforms of edo page mode read-write cycle waveforms of ras -only refresh cycle r o w add ih v il v ih v il v rp (3) t ih v il v i/oh v i/ol v t t asr (8) column address 832l-10 ih v il v cp (43) t asc (10) rcd (6) t t ras (1) t rsh (w)(25) column address t cah (1 1) t cas (5) t cas (5) t t t crp (13) t cah (1 1) t asc (10) t t cwd (38) t lz (21) ih v il v column address t asc (10) rah (9) t wp (29) t cwl (26) t t cwl (26) t r wl (31) t a wd (41) t caa (20) t t o a c (17) t a wd (41) t o a c (17) in t ca c (18) t oed (35) t ds (32) t dh (33) t lz in out hz (22) t oed (35) ds (32) t dh (33) t t cap (43) t t ca c (18) t caa (20) lz in hz (22) t oed (35) ds (32) t dh (33) t t t ca c (18) t caa (20) cap (43) t t wp (29) t t wp (29) t cwl (26) t car (44) t rad (24) ras we oe address t a wd (41) out ra c (19) t o a c (17) t r wd (39) cah (1 1) pcm (50) t t csh (4) t cas (5) t cwd (38) hz (22) cwd (38) out oeh (53) t i/o 1 -i/o 32 cas0-cas3 ih v il v ras ih v il v rp (3) t ih v il v t ras (1) t rc (2) t crp (13) t asr (8) t rah (9) 832l-11 we, oe = don? care note: address row add cas0-cas3 don? care undefined
13 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l waveforms of cas -before- ras refresh counter test cycle waveforms of cas -before- ras refresh cycle ih v il v ih v il v rp (3) t ih v il v t csr (47) t rsh (w)(25) 832l-12 t ras (1) t chr (49) t rcs (7) t wcs (27) t lz (21) ih v il v ih v il v ih v il v t dh (33) t cp (43) t cas (5) t rch (14) t rrh (15) t roh (16) t oac (17) t hz (22) t hz (22) t r wl (31) t cwl (26) t ds (32) ih v il v ih v il v ih v il v read cycle write cycle t wch (28) address we we d out d in ras oe oe i/o 1 -i/o 32 i/o 1 -i/o 32 cas0-cas3 ih v il v ras oh v ol v ih v il v t ras (1) t rc (2) t cp (43) t hz (22) t csr (47) 832l-13 rp (3) t t rpc (48) t chr (49) rp (3) t no te: we, oe , a 0 ? 8 = don? care i/o 1 -i/o 32 cas0-cas3 don? care undefined
14 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l waveforms of hidden refresh cycle (read) waveforms of hidden refresh cycle (write) ih v il v oh v ol v rp (3) t ih v il v t asr (8) t crp (13) t rcd (6) t rsh (r)(12) t rcs (7) 832l-14 t chr (49) t rad (24) t asc (10) t t cah (1 1) row add column address t rrh (15) t oac (17) t lz (21) t hz (22) t hz (22) ih v il v ih v il v ih v il v ras cas0-cas3 we oe i/o 1 -i/o 32 address v alid da t a rah (9) t caa (20) t cac (18) t rac (19) t ras (1) rp (3) t t ras (1) t ar (23) t crp (13) t rc (2) t rc (2) ih v il v ih v il v rp (3) t ih v il v t ras (1) t rc (2) t asr (8) t crp (13) rp (3) t t rcd (6) t rsh (12) t wcs (27) 832l-15 t ras (1) t ar (23) t chr (49) t crp (13) t rad (24) t asc (10) t rah (9) t cah (1 1) row add column address t wch (28) t ds (32) ih v il v ih v il v ih v il v v alid da t a-in t dhr (46) t rc (2) ras we oe address t dh (33) cas0-cas3 i/o 1 -i/o 32 don? care undefined
15 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l waveforms of edo-page-mode read-early-write cycle (pseudo read-modify-write) don? care undefined cas0-cas3 we oe i/o 1 -i/o 32 address ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ras v alid d a t a out 832l-16 v alid d a t a out r o w address column address column address column address v alid d a t a in t ras t csh t crp t rcd t cas t cp t cp t cp t cas t cas t pc t ar t rad t asr t rah t rcs t rch t wcs t caa t caa t ra c t ca c t cap t ca c t coh t ds t dh t oe t wch t cah t asc t cah t asc t cah t asc t car t pc t rsh t rp functional description the v53c832l is a cmos dynamic ram optimized for high data bandwidth, low power applications. it is functionally similar to a traditional dynamic ram. the v53c832l reads and writes data by multiplexing an 18-bit address into a 9-bit row and a 9-bit column address. the v53c832l has four cas inputs. cas 0 con- trols i/o 1 ?/o 8 ; cas 1 controls i/o 9 ?/o 16 ; cas 2 controls i/o 17 ?/o 24 ; and cas 3 controls i/o 23 i/o 32 . these four cas inputs control byte read and byte write. the row address is latched by the row address strobe ( ras ). the column address ?lows through an internal address buffer and is latched by the column address strobe ( cas ). because access time is primarily dependent on a valid column address rather than the precise time that the cas edge occurs, the delay time from ras to cas has little effect on the access time. memory cycle a memory cycle is initiated by bringing ras low. any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. this ensures proper device operation and data integrity. a new cycle must not be initiated until the minimum precharge time t rp /t cp has elapsed. read cycle a read cycle is performed by holding the write enable ( we ) signal high during a ras / cas operation. the column address must be held for a minimum specified by t ar . data out becomes valid only when t oac , t rac , t caa and t cac are all satisifed. as a result, the access time is dependent on the timing relationships between these parameters. for example, the access time is limited by t caa when t rac , t cac and t oac are all satisfied. write cycle a write cycle is performed by taking we and cas low during a ras operation. the column address is latched by cas . the write cycle can be we con- trolled or cas controlled depending on whether we or cas falls later. consequently, the input data must be valid at or before the falling edge of we or cas , whichever occurs last. in the cas -controlled write cycle, when the leading edge of we occurs prior to the cas low transition, the i/o data pins will be in the high-z state at the beginning of the write function. ending the write with ras or cas will maintain the output in the high-z state. in the we controlled write cycle, oe must be in the high state and t oed must be satisfied.
16 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l extended data output page mode edo page operation permits all 512 columns within a selected row of the device to be randomly accessed at a high data rate. maintaining ras low while performing successive cas cycles retains the row address internally and eliminates the need to re- apply it for each cycle. the column address buffer acts as a transparent or flow-through latch while cas is high. thus, access begins from the occur- rence of a valid column address rather than from the falling edge of cas , eliminating t asc and t t from the critical timing path. cas latches the address into the column address buffer. during edo operation, read, write, read-modify-write or read-write- read cycles are possible at random addresses with- in a row. following the initial entry cycle into hyper page mode, access is t caa or t cap controlled. if the column address is valid prior to the rising edge of cas , the access time is referenced to the cas rising edge and is specified by t cap . if the column ad- dress is valid after the rising cas edge, access is timed from the occurrence of a valid address and is specified by t caa . in both cases, the falling edge of cas latches the address and enables the output. edo provides a sustained data rate of 83 mhz for applications that require high bandwidth such as bit- mapped graphics or high-speed signal processing. the following equation can be used to calculate the maximum data rate: data output operation the v53c832l input/output is controlled by oe , cas , we and ras . a ras low transition enables the transfer of data to and from the selected row address in the memory array. a ras high transition disables data transfer and latches the output data if the output is enabled. after a memory cycle is initiated with a ras low transition, a cas low transition or cas low level enables the internal i/o path. a cas high transition or a cas high level disables the i/o path and the output driver if it is enabled. a cas low transition while ras is high has no effect on the i/o data path or on the output drivers. the output drivers, when otherwise enabled, can be disabled by holding oe high. the oe signal has no effect on any data stored in the output latches. a we low level can also disable the output drivers when cas is low. during a write cycle, if we goes low at a time in relationship to cas that would normally cause the outputs to be active, it is necessary to use oe to disable the output drivers prior to the we low transition to allow data in setup time (t ds ) to be satisfied. power-on after application of the v cc supply, an initial pause of 200 m s is required followed by a minimum of 8 initialization cycles (any combination of cycles containing a ras clock). eight initialization cycles are required after extended periods of bias without clocks (greater than the refresh interval). during power-on, the v cc current requirement of the v53c832l is dependent on the input levels of ras and cas . if ras is low during power-on, the device will go into an active cycle and i cc will exhibit current transients. it is recommended that ras and cas track with v cc or be held at a valid v ih during power-on to avoid current surges. table 1. v53c832l data output operation for various cycle types data rate 512 t r c 511 t p c + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = cycle type i/o state read cycles data from addressed memory cell cas -controlled write cycle (early write) high-z we -controlled write cycle (late write) oe controlled. high oe = high-z i/os read-modify-write cycles data from addressed memory cell edo read cycle data from addressed memory cell edo write cycle (early write) high-z edo read-modify-write cycle data from addressed memory cell ras -only refresh high-z cas -before- ras refresh cycle data remains as in previous cycle cas -only cycles high-z
17 v53c832l re v . 1.6 a ugust 1999 mosel vitelic v53c832l package outlines 100-pin pqfp 100-pin tqfp 0.913 +0.008 ?.007 [23.190 ] +0.203 ?.178 0.012 +0.003 ?.002 [0.305 ] +0.076 ?.051 0.787 0.004 [19.990 0.102] 0.551 0.004 [13.995 0.102] 1 30 31 50 51 80 81 100 0.677 0.008 [17.195 0.203] top view 0.113 max [2.87 max] 0.035 0.006 [0.889 0.152] 0.063 typ. [1.600 typ.] 0.134 max. [3.404 max.] unit in inches [mm] 0.010 min. [0.254 min.] 0.004 min. [0.102 min.] see detail ? detail ? gage plane seating plane 0.026 typ. [0.65 typ.] footprint 3.2mm (14x20mm) 0.65 dimensions in millimeters 17.2 0.25 14.00 0.20 23.2 0.25 #1 #100 pin #1 index 0.30 0.08 20.00 a a section: a-a 0.20 0.15 0.05 1.60 0.80 gage plane 1.00 0.15 ref max 0.05 0.10 0.05 1.20
mosel vitelic w orld wide offices v53c832l ?cop yr ight 1998, mosel vitelic inc. 8/99 pr inted in u .s .a. mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u .s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2666-3307 fax: 852-2770-8011 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin rd. science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan wbg marive west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-7125 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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